1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device (EEPROM), such as a flash memory, and a readout method thereof.
2. Description of the Related Art
It is well-known that a plurality of memory cell transistors (called as “memory cells” in the following descriptions) located between bit lines and source lines are series connected to form a NAND string, and a plurality of such NAND strings are highly integrated to form a NAND type non-volatile semiconductor memory device.
For a standard NAND type non-volatile semiconductor memory device, erasing is performed by applying a high voltage, for example 20V, to a semiconductor substrate and 0V to a word line. Therefore, electrons are drawn out from a floating gate which is an electric charge storage layer formed by, for example poly silicon, to make the threshold value lower than the erasing threshold value (for example −3V). On the other hand, for writing (programming), 0V is applied to the semiconductor substrate and a high voltage, for example 20V, is applied to a control gate. Therefore, electrons are injected from the semiconductor substrate to the floating gate to make the threshold value higher than the writing threshold value (for example 1V). The state of the memory cell having one of the above threshold values can be judged by applying a readout voltage (for example 0V) in between the writing threshold value and the erasing threshold value to the control gate and checking if an electric current flows to the memory cell.
Patent document 1: Japan Patent Application Publication No. 2010-287283;
Patent document 2: Japan Patent Application Publication No. 2010-250926.
FIGS. 8A and 8B are section views of a substrate for explaining the problem concerning boosted electrons in the channel of a conventional NAND type flash EEPROM. FIG. 8C is a timing chart of an operation example for explaining the problem concerning boosted electrons in the channel of the NAND type flash EEPROM of FIG. 8A. In the timing charts of the specification, which show operation examples, each line is labeled to show its voltage.
In a preset phase of a readout process, word lines are set at predetermined voltages VpassR (for example 6V) or Vsel (for example 0.5V) before the setting of a readout process (FIGS. 8A and 8C). First, select gate transistors connected to select gate lines SGD and/or SGS are turned off and bit lines are pre-charged to a predetermined value (about 0.5V˜1V). (FIGS. 8A and 8C). Next, in order to reflect the states of the memory cells on the bit line voltage, the select gate transistors connected to the select gate lines SGD and/or SGS are turned on (FIGS. 8B and 8C). At this time, electrons boosted in the substrate 30 flow toward global bit lines GBL and a cell source line SL, and hot electrons 31 are produced in the substrate 30 and injected to the floating gates (FG) (FIG. 8B).
FIGS. 9A and 9B are section views of a substrate for explaining the problem of the case where channel boost of a conventional NAND type flash EEPROM is prevented. FIG. 9C is a timing chart of an operation example for explaining the problem at the time when channel boost of the NAND type flash EEPROM of FIGS. 9A and 9B is prevented.
To prevent channel boost, in the above setup operation for word lines at the voltage VpassR, it is necessary to set both of the select gate lines SGD and SGS to a high level (FIGS. 9A and 41 in 9C), or set all word lines WL and the select gate line SGS to a high level (FIGS. 9B and 42 in 9C). However, in this case, there is a problem where the sensing time required increases. In addition, to prevent electric current from flowing from the global bit lines GBL to the cell source line SL via the memory string, the global bit lines GBL, the select gate line SGD or SGS is necessary to be set at 0V in the setup operation of the word lines WL (42 of FIG. 9C).
The purpose of the invention is to provide a non-volatile semiconductor memory device and a readout method thereof capable of preventing channel boost, preventing current from flowing from the bit lines to the source line, and shortening the sensing time required for data readout.